Semiconductor devices, such as MOS and CMOS integrated circuits, are often damaged by relatively large voltage transients due to Electrostatic Discharge (ESD) and to various spurious high voltage signals. To prevent such failures there is a need for effective protective devices at all MOS inputs. To meet this need, a variety of such protection devices have been suggested and used, such as Zener diodes, forward biased diodes, and MOS transistors.
U.S. Pat. No. 3,748,547 issued on July 24, 1973 to E. Sugimoto teaches the use of a protection PN junction diode connected in parallel with the gate electrode of an FET to protect the gate insulator of the FET in the event that a high voltage pulse is applied to the signal input electrode of the FET.
An article by D. Alameddine, entitled "Protective Circuit for Integrated Semiconductor Devices", published in the IBM Technical Disclosure Bulletin, Vol. 20, No. 10, pages 3962-3963, March 1978, describes another arrangement for protecting the gate inputs of FET circuits and the inputs of bipolar devices. It consists of a double chain of antiparallel diodes having one common pole connected to the input to be protected and another common pole connected to the ground.
CMOS circuits are also susceptible to an undesired SCR action commonly known as "latch-up" which if not controlled can lead to the destruction of the device, or its metal traces, by excessive current flow. This susceptibility is due to the existence within the commonly available CMOS circuits of parasitic PNPN structures. Under certain conditions, such as the presence of a transient signal, one of the PN junctions can be forward biased which can turn-on the SCR action. The device then remains "on" in a latch-up state even after the signal which causes the forward biasing of the PN junction is removed. There have been many efforts to eliminate latch-up in such devices or at the very least to minimize the effects of latch-up on them. Some of these are focused on eliminating latch-up through various fabrication techniques, such as through the use of a dielectric insulator to eliminate the formation of the parasitic bipolar transistors in the devices. Other techniques suggested include the formation of doped regions to reduce the current passage between the parasitic transistors and to reduce their DC current amplification factor.
Thus, CMOS structures are particularly vulnerable to the presence of overvoltage conditions at their input electrodes because such conditions not only can damage the structure's gate dielectric regions but they may also cause a damaging SCR action in the structure. The prior art overvoltage protection structures typically absorb some of these high voltage transient pulses by conducting current into an inactive portion of the substrate. However, such structures may protect the gate dielectric regions of the CMOS structures but occasionally they result in the damage of the structure they protect by creating latch-up conditions in them. For example, the current flowing into the substrate through a protection structure quite often is sufficient to trigger parasitic vertical PNP and lateral NPN transistors to enter into a latch-up condition.
In U.S. Pat. No. 3,934,159 there is shown an IGFET structure having a protective diode designed to avoid the injection of minority carriers into the substrate. However, the particular structure described therein protects the FET devices from overvoltage conditions of a single predetermined polarity. The twin diode protection circuits currently known (such as the one shown in the May/June 1982 issue of "VLSI Design") provide ESD protection but they do not adequately protect the integrated circuits into which they are incorporated from the affects of injections into the common substrate of majority and minority carriers.